# frv testcase for masaccs $ACC40Si,$ACC40Sk # mach: fr400 .include "../testutils.inc" start .global masaccs masaccs: set_accg_immed 0,accg0 set_acc_immed 0x00000000,acc0 set_accg_immed 0,accg1 set_acc_immed 0x00000000,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 0,accg2 test_acc_limmed 0x0000,0x0000,acc2 test_accg_immed 0,accg3 test_acc_limmed 0x0000,0x0000,acc3 set_accg_immed 0,accg0 set_acc_immed 0xdead0000,acc0 set_accg_immed 0,accg1 set_acc_immed 0x0000beef,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 0,accg2 test_acc_limmed 0xdead,0xbeef,acc2 test_accg_immed 0,accg3 test_acc_limmed 0xdeac,0x4111,acc3 set_accg_immed 0,accg0 set_acc_immed 0x0000dead,acc0 set_accg_immed 0,accg1 set_acc_immed 0xbeef0000,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 0,accg2 test_acc_limmed 0xbeef,0xdead,acc2 test_accg_immed 0xff,accg3 test_acc_limmed 0x4111,0xdead,acc3 set_accg_immed 0,accg0 set_acc_immed 0x12345678,acc0 set_accg_immed 0,accg1 set_acc_immed 0x11111111,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 0,accg2 test_acc_limmed 0x2345,0x6789,acc2 test_accg_immed 0,accg3 test_acc_limmed 0x0123,0x4567,acc3 set_accg_immed 0,accg0 set_acc_immed 0x12345678,acc0 set_accg_immed 0,accg1 set_acc_immed 0xffffffff,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 1,accg2 test_acc_limmed 0x1234,0x5677,acc2 test_accg_immed 0xff,accg3 test_acc_limmed 0x1234,0x5679,acc3 set_accg_immed 0,accg0 set_acc_immed 0x12345678,acc0 set_accg_immed 0xff,accg1 set_acc_immed 0xffffffff,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set test_accg_immed 0,accg2 test_acc_limmed 0x1234,0x5677,acc2 test_accg_immed 0,accg3 test_acc_limmed 0x1234,0x5679,acc3 set_spr_immed 0,msr0 set_accg_immed 0x7f,accg0 set_acc_immed 0xfffe7ffe,acc0 set_accg_immed 0x0,accg1 set_acc_immed 0x00020001,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set test_accg_immed 0x7f,accg2 test_acc_limmed 0xffff,0xffff,acc2 test_accg_immed 0x7f,accg3 test_acc_limmed 0xfffc,0x7ffd,acc3 set_spr_immed 0,msr0 set_accg_immed 0x80,accg0 set_acc_immed 0x00000001,acc0 set_accg_immed 0xff,accg1 set_acc_immed 0xfffffffe,acc1 masaccs acc0,acc2 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set test_accg_immed 0x80,accg2 test_acc_limmed 0x0000,0x0000,acc2 test_accg_immed 0x80,accg3 test_acc_limmed 0x0000,0x0003,acc3 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_accg_immed 0,accg0 set_acc_immed 0x00000001,acc0 set_accg_immed 0,accg1 set_acc_immed 0x00000001,acc1 set_accg_immed 0,accg2 set_acc_immed 0x00000001,acc2 set_accg_immed 0x7f,accg3 set_acc_immed 0xffffffff,acc3 masaccs.p acc0,acc0 masaccs acc2,acc2 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set test_spr_bits 2,1,1,msr1 ; msr1.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set test_accg_immed 0,accg0 test_acc_limmed 0x0000,0x0002,acc0 test_accg_immed 0,accg1 test_acc_limmed 0x0000,0x0000,acc1 test_accg_immed 0x7f,accg2 test_acc_limmed 0xffff,0xffff,acc2 test_accg_immed 0x80,accg3 test_acc_limmed 0x0000,0x0002,acc3 pass